The present invention generally relates to a method for forming a dielectric material layer in an electronic structure and the structure formed and more particularly, relates to a method for forming a porous dielectric material layer in an electronic structure by first forming a non-porous dielectric material layer then partial curing, patterning, and final curing the layer at a higher temperature than that used in the partial curing to transform the non-porous dielectric material into a porous dielectric material, and electronic structure formed by such material.
In the recent development of semiconductor devices, the continuing miniaturization of the devices demands the use of electronic materials of more superior properties. For instance, the dielectric material used as an insulating layer in a semiconductor device, must have a lower dielectric constant in order to provide a smaller signal propagation delay. It is therefore important to provide electronic materials that have superior insulating properties, such as a reduced dielectric constant for current and future semiconductor device applications.
One of the solutions in providing a dielectric material layer that has improved insulating property, i.e. a lower dielectric constant, is to use a dielectric material that contains voids. A void-filled, or porous dielectric material has a lower dielectric constant than the fully dense void-free version of the same material. However, problems arise in utilizing porous dielectric materials, i.e. when these materials are first formed in an electronic device and then are subjected to a patterning process by reactive ion etching (RIE). The very nature of the desirable porous structure of these materials subject them to excessive etching when exposed to etch gasses utilized in the reactive ion etching process. One solution proposed to solve this problem is to select low-k dielectric materials that have closed porosity. However, any attempt to slice a closed pore material exposes open pores on a new cut surface. Thus, the pores exposed in such a new cut surface would still be subjected to attack by the etch gas used in the reactive ion etching process for patterning the dielectric material layer.
It is therefore an object of the present invention to provide a method for forming a porous dielectric material layer in an electronic structure that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming a porous dielectric material layer in an electronic structure that is not subjected to attack by reactive ion etching gases during a patterning process.
It is a further object of the present invention to provide a method for forming a porous dielectric material layer in an electronic structure by first forming a non-porous dielectric material layer, patterning the layer in a reactive ion etching process and then forming pores in the dielectric material layer.
It is another further object of the present invention to provide a method for forming a porous dielectric material layer in an electronic structure by first patterning a non-porous dielectric material layer and then forming pores after the patterning process.
It is still another object of the present invention to provide a method for forming a porous dielectric material layer in an electronic structure by first depositing a non-porous dielectric material layer, partially curing the layer at a first low temperature, patterning the non-porous dielectric material layer, and then forming pores and transforming the material layer into a porous structure at a second high curing temperature.
It is yet another object of the present invention to provide a method for forming a porous dielectric material layer in an electronic structure by transforming a dual-phase material into a single-phase, void-filled material at a high curing temperature.
It is still another further object of the present invention to provide an electronic structure that has a layer of porous dielectric material formed therein wherein the layer of porous material has a porosity between about 0.1 vol. % and about 50 vol %.
It is yet another further object of the present invention to provide an electronic structure that has a layer of porous dielectric material formed therein for electrical insulation wherein the porous dielectric material has a dielectric constant between about 1 and about 3.
In accordance with the present invention, a method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed.
In a preferred embodiment, a method for forming a porous dielectric material layer in an electronic structure can be carried out by the steps of providing a pre-processed electronic substrate, depositing a layer of non-porous dielectric material on top of the pre-process electronic substrate, curing the electronic substrate at a first temperature typically about 250xc2x0 C., defining and patterning the layer of non-porous dielectric material, and curing the electronic substrate at a second temperature higher than the first temperature (typically about 350xc2x0 C. to about 450xc2x0 C.) transforming the non-porous dielectric material into a porous dielectric material.
In the method for forming a porous dielectric material layer in an electronic structure, the non-porous dielectric material is substantially a dual-phase material while the porous dielectric material is substantially a single-phase material. The non-porous dielectric material may be a physical mixture of a thermally labile material and a thermally stable material. The thermally stable material sets into a solid at the first curing temperature, and the thermally labile material decomposes and volatilizes at the second curing temperature. The method may further include the step of forming a mask layer on top of the layer of non-porous dielectric material, or the step of forming the mask layer of at least one material selected from the group consisting of SiO2, Al2O3, Si3N4, SiC and SiCOH. The method may further include the step of forming the mask layer to a thickness of not greater than 100 nm. The method may further include the step of providing a pre-processed silicon wafer.
The first temperature used may be between about 100xc2x0 C. and about 350xc2x0 C., the second temperature used may be greater than 250xc2x0 C. and higher than the first temperature. The method may further include the step of photolithographically defining and patterning the layer of non-porous dielectric material, or the step of depositing the non-porous dielectric material by a spin coating method. The porous material formed may have a porosity of between about 0.1 vol. % and about 50 vol. %, or preferably a porosity between about 5 vol. % and about 30 vol. %. The method may further include the step of depositing the layer of non-porous dielectric material to a thickness between about 100 nm and about 1000 nm. The non-porous dielectric material deposited may include methyl silsesquioxane (MSSQ), hydrogen silsesquioxane (HSQ), silica and aromatic thermoset polymers such as the SiLK(copyright) Semiconductor Dielectric or Flare(copyright) and at least one pore generating labile material or porogen of polymeric nature.
In another preferred embodiment, a method for forming a void-filled dielectric material layer in an electronic structure may be carried out by the operating steps of providing an electronic structure that has devices built on top, depositing a layer of a dual-phase dielectric material consisting of a thermally stable material and a thermally labile material on top of the electronic structure, annealing the electronic structure at a first temperature between the setting temperature of the thermally stable material and the decomposition temperature of the thermally labile material, photolithographically defining and patterning the dual-phase dielectric material, and annealing the electronic structure at a second temperature not less than the decomposition and volatilization temperature of the thermally labile material forming a single-phase, void-filled dielectric material.
In the method for forming a void-filled material layer in an electronic structure, the first temperature may be a temperature between about 100xc2x0 C. and about 350xc2x0 C., the second temperature may be greater than about 250xc2x0 C. and higher than the first temperature. The thermally stable material sets into a solid at the first annealing temperature, while the thermally labile material volatilizes at the second annealing temperature. The method may further include the step of forming a mask layer on top of the layer of dual-phase dielectric material. The method may further include the step of forming the mask layer of at least one material selected from the group consisting of SiO2, Al2O3, Si3N4, SiC and SiCOH. The method may further include the step of forming the mask layer to a thickness of not greater than 100 nm. The first temperature-utilized may be between about 100xc2x0 C. and about 350xc2x0 C., the second temperature utilized may be greater than 250xc2x0 C. and higher than the first temperature. The method may further include the step of depositing the layer of dual-phase dielectric material by a spin coating technique to a thickness between about 100 nm and about 1000 nm. The single-phase, void-filled dielectric material may contain voids of between about 0.1 vol. % and about 50 vol. %, and preferably between about 5 vol. % and about 30 vol. %.
The present invention is further directed to an electronic structure that has a layer of porous dielectric material formed therein for electrical insulation which includes a pre-processed electronic substrate, a layer of porous dielectric material that has a porosity between about 0.1 vol. % and about 50 vol. % formed and patterned on the pre-processed electronic substrate, and a conductive metal filling the pattern formed in the layer of porous dielectric material.
In the electronic structure that has a layer of porous dielectric material formed therein for electrical insulation, the porous dielectric material has a dielectric constant of between about 1 and about 3, or preferably between about 1.3 and about 2.6. The conductive metal forms an interconnect between two conductive regions in the electronic structure, the conductive metal may also form an interconnect in a single damascene structure in a semiconductor device, or a dual damascene structure in a semiconductor device. The conductive metal may be copper, aluminum, or other metals such as silver, gold and alloys thereof.